1. Field of Invention
This invention is in the field of computer electronics and methods therefor and, more particularly, relates to apparatus and methods for causing a gate to have a selectable gate delay and method therefor.
2. Description of the Prior Art
The linchpin of a modern computer is a clock that provides clock pulses at a known frequency. Operation of components of the computer are typically synchronized to an edge of a clock pulse. A memory unit of the computer, for example, includes a plurality of binary storage elements where a signal representation of a number is stored by changing the state of some of the elements when the edge of the clock pulse occurs.
It should be understood that the components have respective clock input signal lines whereon the clock provides the clock pulses, thereby achieving the synchronous operation referred to hereinbefore. Similar to the memory unit, all of the components can only change state when the edge of the clock pulse occurs.
The clock lines have respective capacitances that load the clock. The loading may cause a distortion of the wave form of the clock pulse that results in improper operation of the components. The improper operation may be obviated by altering the duty cycle of the clock pulse to provide increased time for charging, or discharging, of the line capacitances during a portion of a clock cycle.
It is often desirable to provide a plurality of trains of pulses derived from the clock. Although each of the pulse trains has the same frequency, there is a known phase difference between the pulse trains. The plurality of pulse trains is provided by what is known as a multiphase clock, with a pulse train thereof being known as a phase of the multiphase clock.
With the multiphase clock, input/output (I/O) circuitry, for example, and an application specific integrated circuit (ASIC) may be synchronized to different phases of the multiphase clock, thereby causing a separation between the times that the I/O circuitry and the ASIC can change states. Additionally, phases of the multiphase clock may be logically combined to provide the clock pulse with the altered duty cycle.
Phases of the multiphase clock are usually generated by applying the clock pulses to a signal input of a shift register. Additionally, a shift register clock pulse train is provided to a clock input of the shift register. Outputs of stages of the shift register respectively generate phases of the multiphase clock. When it is desired to have the phase delay between phases of the multiphase clock resolvable to one nanosecond, the shift register clock pulses are at a frequency of at least one gigahertz.
As known to those skilled in the art, the shift register is necessarily of a type that has an undesirably high power consumption and is costly because the shift register clock has the one gigahertz frequency. Heretofore, there has not been an efficient, simple, economical way of generating high resolution phases of the multiphase clock.